Miniaturization of semiconductor elements has resulted in continued improvement in the performance of MOS transistors for a long time. In recent years, expected improvement in the performance of MOS transistors has not been obtained despite continued miniaturization of semiconductor elements.
One of the causes is a reduction in the carrier mobility of a MOS transistor due to the introduction of impurities to a portion directly under a gate in order to control thresholds of the miniaturized MOS transistor. Furthermore, an increase in electric field intensity with a thinner gate insulating film results in more carriers colliding with the gate insulating film. This results in an increase in the number of carriers scattered by irregularities of the gate insulating film, thereby reducing carrier mobility.
It has been reported that to improve carrier mobility in a MOS transistor, the crystal lattice of a substrate is strained in a channel region directly under a gate with a material such as silicon oxide producing strain (for example, Japanese Laid-open Patent Publication No. 2004-235332).
The direction of strain for improving carrier mobility differs between an N-type MOS transistor utilizing electrons as carriers and a P-type MOS transistor utilizing holes as carriers. Thus, when the mobility of one type of carriers is increased by the same type of strain acting on the active regions, the mobility of the other type of carriers is reduced.
It has been reported that a semiconductor device has a structure such that the mobility of one type of carriers for an N-type MOS transistor and a P-type MOS transistor is increased and such that a reduction in the mobility of the other is prevented.
According to the above-described document, the semiconductor device has an active region including the N-type MOS transistor, and an active region including the P-type MOS transistor, and grooves for isolating these active regions. With respect to the groove surrounding the N-type MOS transistor, sections of the groove parallel and perpendicular to the direction in which a source subregion and a drain subregion are connected are filled with an oxidation preventive film (e.g., silicon nitride) and a material composed of a silicon oxide film producing strain. With respect to the groove surrounding the P-type MOS transistor, sections of the groove parallel to the direction in which a source subregion and a drain subregion are connected are filled with an oxidation preventive film and a material composed of silicon oxide producing strain. Sections of the groove perpendicular to the direction in which the source subregion and the drain subregion are connected are filled with silicon oxide alone. No stress is applied to the active region of the N-type MOS transistor because silicon oxide does not grow in the subsequent oxidation treatment. On the other hand, a compressive stress is applied to the active region of the P-type MOS transistor because silicon oxide grows in the sections of the groove perpendicular to the direction in which the source subregion and the drain subregion are connected. Thereby, a reduction in electron mobility is prevented, and the hole mobility is improved (for example, Japanese Laid-open Patent Publication No. 2003-158241).
In the arrangement of the material producing strain described in Patent Document 2, the strain produced in the active region of the MOS transistor is determined only by the property of one type of material producing strain. Thus, it is difficult to adjusting the strain produced in the active region to a target state.
In the case where unevenness in the amount of change in electrical properties occurs even when a constant strain is produced in the active region of the MOS transistor, disadvantageously, the unevenness in the electrical properties of the MOS transistor cannot be prevented.
Disadvantageously, the strain produced in the active region of the MOS transistor cannot be controlled so as to be larger than the strain determined only by the property of one type of material producing strain.